Description
The MVD DVB-CSA Descrambler core allows to decrypt MPEG-TS stream using ETSI specified DVB Common Scrambling Algorithm (CSA2).
Important note
We
are only able to license this IP core to customers that have signed the
ETSI Non-Disclosure Agreement and are in possession of a valid license
to use the Common Scrambling Algorithm.
This is a
requirement on all users of this technology, applied by the consortium
who own the rights to the algorithm. Please feel free to contact MVD
for more information on this requirement.
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Features
- Drop-in module for Spartan™-6, Virtex™-6, Artix™-7, Kintex™-7, Virtex™-7 FPGAs and Zynq™
- DVB/ATSC compliant
- Manage automatically odd/even key encryption
- Selection of up to 64 PIDs and 64 Keys (32ODD/32EVEN) at the same time (any PID can use any key)
- Automatically removing of encryption flags of MPEG-TS packet header
- Supports 188, 204 and 208 bytes packet input
- Supports Data Packet or Data Burst format
- Full synthesizable RTL VHDL design (not delivered) for easy customization
- Design delivered as Netlist
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DVB-CSA Descrambler
