Description
The UDP/IP core is a drop-in module which includes
its own MAC to send and receive UDP packets on an Ethernet network.
Applications
The UDP/IP core can be used in applications related to Ethernet transmission:
- voice over IP (VoIP)
- television over
IP (IPTV)
- fast transmission of large amounts of data
(medical imaging, etc)
|
 |
|
Features
- Drop-in module for Spartan™-6, Virtex™-7, Artix™-7, Kintex™-7 an Zynq™ Xilinx FPGAs
- GMII default interface (GMII-to-RGMII option / SGMII with Xilinx Logicore IP Ethernet 1000BASE-X PCS/PMA or SGMII)
- MAC Layer is included in the core (support of Ethernet Frame II)
- Ethernet 100/1000 or 10G/25G
- Supported protocols :
- IPv4
- UDP
- ARP (for Request and Reply)
- ICMP
- IGMPv3 (supports IGMPv2 for backward compatibility)
- DHCP client
- VLAN Rx / Tx (supports IEEE 802.1 Q Frame)
- IPv4 fragmentation not supported
- Support up to 8 Multicast addresses for Reception
(can be increased if needed but will require more FPGA resources)
- Netlists delivered for 1, 2, 4, 8, 16, 24 and 32 transmit UDP channels
- Management of ARP table up to UDP output channels count
(if UDP output channels count >= 2)
- Point to Point UDP Transmission Channel for well known link
- Jumbo frames up to 9kB (requires FPGA internal memory, delivered on demand)
- Raw Frames (requires FPGA internal memory, delivered on demand)
- Differential Services (QoS) programmable for each UDP transmit channel
- TTL IP Layer programmable for each UDP transmit channel
- Support up to 8 different VLAN ID tag for Ethernet Reception
(can be increased if needed)
- Support up to 8 different VLAN ID tag for for each UDP transmit channel
(can be increased if needed)
- Netlist version available for ISE and VIVADO
|
Full Hardware UDP/
IP stack
