Description
The MVD DVB Remultiplexer core
analyses each MPTS/SPTS stream input and gives access to the followings
information and statistics:
- Incoming TS Stream features (TS_ID, Version,
Tables, ...)
- Incoming/ Payload/ Outcoming rates
- Program List and bandwidth for each program.
- Program Information (Names)
Then, it filters user selected
programs and regenerates PSI/SI tables such as PAT, SDT, NIT (according
to programmed mode), PMTs, EITs (according to configuration).
TOT, TDT, are filtered and
generated thanks to the UTC70 input port. Not filtered PMT programs and
others PID which do not correspond to any program or PSI/SI tables are
passed through.
EIT and PMTs are re-generated
according to the modifications to apply to the output stream.
BAT and RST are filtered. CAT
and related PIDs are filtered according to the configuration of the
remultiplexer.
The DVB Remultiplexer core
allows the filtering of programs of DVB MPEG TS flows compliant with
the standards :
- UIT-T H222 (02/00) / ISO13818-1
- ETSI EN 300 468 v1.8.1 (2008-7)
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Features
- Supported FPGA families:
Spartan®-6, Virtex®-6/7, Kintex™-7, Artix™-7, Zynq™
- N SPI input / M SPI output (N and M from 1 to 8)
- Adapt one or several MPTS/SPTS stream into
one or several MPTS by filtering and multiplexing complete services
- SFN MIP table insertion independent for each
output (for DVB-T core control)(optional)
- Management of PSI/SI tables (automatic tables
generator) according to ETS300468 and ISO 13818-1.
- Configurable via an RS232 link or I˛C link
- Service filtering and insertion of custom NIT
- Full PCR re-stamping
- Master/Slave control of input/output mux flows
- Statistical service bandwidth estimation per
input
- Maximize output payload bandwidth thanks to
smoothing FIFO.
- Common
output Smoothing FIFO can be implemented as block RAM, external
Synchronous SRAM memory or external DDR3 (same memory than program
memory)
- Size of the output smoothing FIFO is
configurable and common for all output channels..
- Full synthesizable RTL design (not delivered)
for easy customization
- Netlist version available for ISE and VIVADO
- CPU Interface to control MVD Modulator CORE
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