Publications |
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MVD Cores presentation |
 |
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Analog Devices' FMC boards
support Xilinx's FPGA targeted design platforms
to help designers reduce developement time
www.analog.com
January 2012 |
 |
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"A simple and effective
method to implement DSP functions in an
FPGA" (french)"
Electronique
Le mensuel des ingénieurs de conception
December 2005 |
 |
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"Writing RTL Code for
Virtex-4 DSP48 blocks with XST 8.1i"
Xcell Journal
4th quarter 2005 |
 |
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"Bien concevoir avec un
FPGA"(french)
Electronique Mensuel
May 2002 |
 |
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Presentation of an image
processing technique in FPGA (french).
Electronique Mensuel
November 2001 |
 |
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"Implementing histogram for
image processing"
Implementation of an histogram calculation in
real-time, specific to Virtex and Spartan II.
Xilinx Xcell
Winter 2000 |
 |
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"Creating finite state
machines"
An original technique of development permitting
an increase in both density and results of your
designs. Takes advantage of Virtex and Spartan II
architectures.
Xilinx Xcell
Winter 2000 |
 |
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"Using SpartanXL for
Low-cost Video Applications"
Image processing and design tutorial.
XCELL 32
2nd quarter 1999 |
 |
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ANNA-LIZ - A new core for
debugging PCI designs
A new concept at the time of publication :
use of FPGAs memory for logical analysis and
debugging. |
 |
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"A PCI Acquisition Board
Using the XC4013"
Design example of PCI bus for high-speed
acquisition.
XCELL 31
1st quarter 1999
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 |
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