Description
The MVD MPEG TS Deserializer
core is a drop-in module that includes the following functions:
- Data acquisition on clock
- Serial/parallel Conversion
- Auto adaptation to 188/204 bytes packet Input
- 188 bytes MPEG-TS output
- No decoding control
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![](design/separ_orange.gif) |
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Features
- Drop-in module for
Spartan-3™, Spartan-6™, 7-Series™ FPGAs
- Full synthesizable RTL VHDL
design (not delivered) for easy customization
- Design delivered as Netlist
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