MPEG TS Deserializer
     
         
  The MPEG TS Deserializer converts a serial MPEG TS input stream into a parallel MPEG TS output stream. MPEG TS Deserializer block diagram  
         
Description

The MVD MPEG TS Deserializer core is a drop-in module that includes the following functions:
    • Data acquisition on clock
    • Serial/parallel Conversion
    • Auto adaptation to 188/204 bytes packet Input
    • 188 bytes MPEG-TS output
    • No decoding control
    		  Features
    • Drop-in module for Spartan-3™, Spartan-6™, 7-Series™ FPGAs
    • Full synthesizable RTL VHDL design  (not delivered) for easy customization
    • Design delivered as Netlist
    Applications

    MVD MPEG TS Deserializer may be used in applications related to DVB/MPEG transport streams for Satellite tuner data de-serialization.    		    
    Documentation
    Product brief        
    Data sheet        
    Application note "From MPEG-TS to RF"
               
    Contact
    Sales: info_cores@mvd-fpga.com
    Technique: support_cores@mvd-fpga.com