Description
The MVD ASI receiver core is a drop-in
module for FPGA that includes the
following functions:
- Clock/Data recovery
- Serial/parallel Conversion
- Sync Byte (FC Comma Detection)
- 8B/10B decoding
- Auto adaptation to 188/204 bytes
packet Input
- 188 bytes MPEG-TS output
- Optional frame buffer
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Features
- Multi mode ASI receiver
- European standard EN50083-9 Annex
B
- Supported FPGA families: Spartan®-6, Virtex®-6/7, Kintex™-7, Artix™-7, Zynq™
- 27MHz Single Clock
- Supports 188 or 204 bytes packet
input
- Supports direct ASI interface
(clock recovery from\par Data)
- Supports Data Packet or Data
Burst format
- Input can be standard I/O or Transceiver I/O (GTP, GTH, GTY, GTX)
- Single channel - support for
multi channel
- Full synthetizable RTL VHDL
design (not delivered) for easy
customization
- Design delivered as Netlist
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ASI receiver
